1. Field of the Invention
This invention relates to update mechanisms for storage arrays on an integrated circuit and more particularly to an update mechanism for a branch prediction array embodied on a superscalar microprocessor.
2. Description of the Relevant Art
Integrated circuits are groups of transistors employed on a single monolithic substrate. The groups of transistors embody various functions for a system (for example, a computer system). One particular example of an integrated circuit is a superscalar microprocessor which embodies multiple instruction processing pipelines. Integrated circuits typically have a clock input associated with them, which defines a "clock cycle". A clock cycle is an interval of time in which the functions embodied on the integrated circuit complete a portion of their tasks (a "subfunction"). At the end of a clock cycle, the results are moved to the next function or subfunction which operates on the value.
Integrated circuits may employ arrays for storing information useful to the embodied functions. For example, data and instruction caches are arrays that are commonly employed within superscalar microprocessors. As used herein, the term "array" means a plurality of storage locations configured into a structure from which the values stored in one or more of the plurality of storage locations may be selected for manipulation. Arrays are configured with one or more input ports which allow functions to access information stored in the array. Each input port may be associated with an output port. A particular input port may allow read access, write access, or read/write access to storage locations within the array and is referred to as a read port, a write port, or a read/write port, respectively. A read access is an access in which the value in the selected storage location is transferred to the associated output port and the storage location is left unchanged. A write access is an access in which the value in the selected storage location is changed to a value provided with the input port. A port which allows read/write access allows either a read or a write access to occur. Ports which allow write accesses typically are associated with a write data input port. The write data input port conveys the data to be stored at the address provided on the write port.
"Indexes" are often used to select a storage location within an array. An index is a value which indicates which of the plurality of storage locations of an array that a particular access intends to manipulate. The act of selecting one of a plurality of storage locations according to an index is called "indexing". In one particular example, a set associative cache has an index which identifies which group of sets to access and a "way value" which selects one of the sets within the selected group for manipulation.
In many cases, more than one access to an array in a given clock cycle may be desirable for the functions an integrated circuit embodies. An array which allows two accesses per clock cycle is referred to as "dual-ported". Each port may allow a read access, a write access, or a read/write access. Unfortunately, dual-ported arrays are much larger than single ported arrays, often occupying more than double the silicon area of a single ported array which stores the same amount of information.
One particularly useful dual-ported array is an array in which one port allows a read access while a second (write) port updates a storage location with new information. Arrays that are configured in this way do not block a read access with an update, which simplifies array control logic and may improve performance. An example of an array configured with a read port and a write port for updates is a branch prediction array associated with a branch prediction unit of a superscalar microprocessor. The branch prediction array stores information related to past branch predictions. A fetch address is used to index into the branch prediction array, and the information read from the array is used to create a branch prediction associated with the instructions residing at the fetch address. When a branch instruction is mispredicted, then the correct address is fetched and new prediction information is calculated. The new prediction information should be stored into the branch prediction array in a storage location indexed by the address of the mispredicted branch instruction. Then, the next time the branch instruction is fetched, a correct prediction may be made. The new prediction information is available to update the branch prediction array in the clock cycle following the cycle in which the correct address is fetched. However, the clock cycle that the update is available is also a clock cycle in which a fetch address is presented to the branch prediction unit. Therefore, a read port for the fetch address and a write port for the update would be useful for the branch prediction array, but the silicon area cost for the dual-ported array is relatively large. A mechanism which achieves the effects of a dual-ported array with a read port and a write port without the associated silicon area penalty is desired.